将一阶逻辑转换为 Prolog

Convert first order logic into Prolog

我需要将以下 FOL 句子表述为 Prolog 规则，但完全不知道如何做到这一点。 (我是 Prolog 的新手)：

"如果两个终端相连，则它们具有相同的信号。"
在一阶逻辑中，这将是：

1	FORALL(T1, T2) : Terminal(T1) AND Terminal(T2) AND Connected(T1, T2) => Signal(T1) = Signal(T2)

我知道，"and"是如何用 Prolog 编写的，而且你不需要 FORALL。我的问题是，左侧只能是一个谓词。
这是一个更大问题的一部分，完整的规则集将是：

如果两个端子相连，则它们具有相同的信号

连通是可交换的

每个终端的信号不是 1 就是 0

有四种类型的门(and, or, xor, neg)

当且仅当其任何输入为 0 时，与门的输出为 0

当且仅当它的任何输入为 1 时，或门的输出为 1

当且仅当输入不同时，异或门的输出为 1

否定门的输出与输入不同

门(除了 neg)有两个输入和一个输出

一个电路的输入和输出数量达到了它的极限，没有任何东西超出它的数量

Gates、terminals、signals、gate types和Nothing都是不同的

门是电路

我目前正在制定规则，我会在完成后立即发布。这是我到目前为止所拥有的(第一行 % 是自然语言，第二行 % 是直观的 FOL 表示，之后的行是我对 Prolog 规则的尝试)：

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%If two terminals are connected, then they have the same signal:
%all(T1, T2) : terminal(T1), terminal(T2), connected(T1, T2) => signal(T1) = signal(T2).
same_value(T1, T2) :- terminal(T1), terminal(T2), connected(T1, T2).

%Connected is commutative:
%all(T1, T2) :- connected(T1, T2) <=> connected(T2, T1).
connected(T1, T2) :- connected(T2, T1).

%The signal at every terminal is either 1 or 0:
%all(T) :- terminal(T) => signal(T) == 1; signal(T) == 0.
terminal(T) :- signal(T) = 1; signal(T) = 0.

%There are four types of gates:
%all(G) :- (gate(G), K = type(G)) => (K == and; K == or; K == xor; K == neg).

%An and gate's output is 0 if and only if any of its inputs is 0:
%all(G) :- gate(G), type(G) == and => signal(out(1, G)) = 0 <=> some(N), signal(in(N, G)) == 0.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 0; signal(in(2, G)) == 0) => 0.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 1, signal(in(2, G)) == 1) => 1.
%this produces an error: Operator expected

%An or gate's output is 1 if and only if any of its inputs is 1:
%all(G) :- gate(G), type(G) == or => signal(out(1, G)) = 1 <=> some(N), signal(in(N, G)) == 1.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 0, signal(in(2, G)) == 0) => 0.
signal(out(1, G)) :- (gate(G), type(G) == or, signal(in(1, G)) == 1; signal(in(2, G)) == 1) => 1.
%this produces an error: Operator expected

%An xor gate's output is 1 if and only if its inputs are different:
%all(G) :- gate(G), type(G) == xor => signal(out(1, G)) = 1 <=> signal(in(1, G)) \\= signal(in(2, G)).
signal(out(1, G)) :- (gate(G), type(G) == xor, signal(in(1, G)) == signal(in(2, G))) => 0.
signal(out(1, G)) :- (gate(G), type(G) == xor, signal(in(1, G)) \\= signal(in(2, G))) => 1.
%this produces an error: Operator expected

%A neg gate's output is different from its input:
%all(G) :- gate(G), type(G) == neg => signal(out(1, G)) = not(signal(in(1, G))).
signal(out(1, G)) :- (gate(G), type(G) == neg, signal(in(1, G)) == 1) => 0.
signal(out(1, G)) :- (gate(G), type(G) == neg, signal(in(1, G)) == 0) => 1.
%this produces an error: Operator expected

%The gates (except for neg) have two inputs and one output:
%all(G) :- gate(G), type(G) == neg => arity(G, 1, 1).
%all(G) :- gate(G), K = type(G), (K == and; K == or; K == xor) => arity(G, 2, 1).
arity(G, 1, 1) :- gate(G), type(G) == neg.
arity(G, 2, 1) :- gate(G), (type(G) == and; type(G) == or; type(G) == xor).

%A circuit has terminals up to its input and output arity, and nothing beyond its arity:
%all(C, I, J) :- circuit(C), arity(C, I, J) =>
% all(N), (N =< I => terminal(in(C, N))), (N > I => in(C, N) = nothing),
% all(N), (N =< J => terminal(out(C, N))), (N > J => out(C, N) = nothing).

%Gates, terminals, signals, gate types, and Nothing are all distinct:
%all(G, T) :- gate(G), terminal(T) => G \\= T \\= 1 \\= 0 \\= or \\= and \\= xor \\= neg \\= nothing.

%Gates are circuits:
%all(G) :- gate(G) => circuit(G).
circuit(G) :- gate(G).